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Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs

Authors:
Ekawat Homsirikamol
Marcin Rogawski
Kris Gaj
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DOI: 10.1007/978-3-642-23951-9_32
URL: https://www.iacr.org/archive/ches2011/69170491/69170491.pdf
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Conference: CHES 2011
BibTeX
@inproceedings{ches-2011-24090,
  title={Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs},
  booktitle={CHES},
  series={Lecture Notes in Computer Science},
  publisher={Springer},
  volume={6917},
  pages={491-506},
  url={https://www.iacr.org/archive/ches2011/69170491/69170491.pdf},
  doi={10.1007/978-3-642-23951-9_32},
  author={Ekawat Homsirikamol and Marcin Rogawski and Kris Gaj},
  year=2011
}