CryptoDB
RISC-V Scalar Crypto
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| Presentation: | Slides |
| Abstract: | The initial cryptographic instruction set extension of RISC-V is looking stable and is approaching a specification freeze. Implementations exist and evaluation is ongoing on multiple fronts. In this talk, we discuss lightweight, ``scalar crypto''' instructions that have been introduced to the specification during the past year. These instructions directly extend the base RV32 and RV64 instruction set, removing the requirement of implementing a vector or SIMD unit. We hope that this makes RISC-V even more attractive for embedded chip vendors. We describe how AES, SHA2/3, and GCM can be implemented and optimized with base 32/64-bit register file, and how Entropy Sources are accessed to build hardware TRNGs. We also give pointers on efficient asymmetric (ECC, RSA, PQC) implementations on such targets, and describe how tightly-coupled custom accelerators and side-channel mitigations can be integrated. |
| Video: | https://youtu.be/kO-3Uh7tq60?t=897 |
BibTeX
@misc{rwc-2021-35539,
title={RISC-V Scalar Crypto},
note={Video at \url{https://youtu.be/kO-3Uh7tq60?t=897}},
howpublished={Talk given at RWC 2021},
author={Markku-Juhani Saarinen and Ben Marshall},
year=2021
}