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An Optimized S-Box Circuit Architecture for Low Power AES Design

Authors:
Sumio Morioka
Akashi Satoh
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DOI: 10.1007/3-540-36400-5_14
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Conference: CHES 2002
BibTeX
@inproceedings{ches-2002-728,
  title={An Optimized S-Box Circuit Architecture for Low Power AES Design},
  booktitle={Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers},
  series={Lecture Notes in Computer Science},
  publisher={Springer},
  volume={2523},
  pages={172-186},
  doi={10.1007/3-540-36400-5_14},
  author={Sumio Morioka and Akashi Satoh},
  year=2002
}