International Association
for Cryptologic Research

Billions of devices running the RISC-V Open Source ISA have been shipped, and an increasing number of those implement cryptography instructions from the Cryptography Extensions Task Group (CETG). As a significant development, the RISC-V Android platform requires a CPU with vector cryptography extensions. We describe RISC-V extensions currently being developed for High Assurance and Post-Quantum Cryptography.

Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE. We survey the state-of-the-art industrial and academic ISEs for AES, implement and evaluate five different ISEs, one of which is novel. We recommend separate ISEs for 32 and 64-bit base architectures, with measured performance improvements for an AES-128 block encryption of 4x and 10x with a hardware cost of 1.1K and 8.2K gates respectively, when compared to a software-only implementation based on use of T-tables. We also explore how the proposed standard bit-manipulation extension to RISC-V can be harnessed for efficient implementation of AES-GCM. Our work supports the ongoing RISC-V cryptography extension standardisation process.